This chapter is from the book
This chapter is from the book
This chapter is from the book
Packaging Modules
We've discussed how memory chips work on the inside, but you'll need to know how these chips are installed on a motherboard. Once again, most of the changes came about either to make maintenance easier, or to avoid bad connections. Keep in mind that installing a combined "unit" or module of some kind is less expensive than having many individual units to install.
Dual Inline Package (DIP)
Originally, DRAM came in individual chips called dual inline packages (DIPs). XT and AT systems had 36 sockets on the motherboard, each with one DIP per socket. Later, a number of DIPs were mounted on a memory board that plugged into an expansion slot. It was very time-consuming to change memory, and there were problems with chip creep (thermal cycling), where the chips would work their way out of the sockets as the PC turned on and off. Heat expanded and contracted the sockets, and you'd have to push the chips back in with your fingers.
To solve this problem, manufacturers finally soldered the first 640 kilobytes of memory onto the board. Then the problem was trying to replace a bad chip. Finally, chips went onto their own card, called a single inline memory module or SIMM. On a SIMM, each individual chip is soldered onto a small circuit board with an edge connector (Holy Pentium II architecture, Batman!).
Connectors: Gold Vs. Tin
SIMMs and DIMMs come with either tin (silver-colored) or gold edge connectors. Although you may assume that gold is always better, that's not true. You want to match the metal of the edge connectors to the metal in the board's socket. If the motherboard uses gold sockets, use a gold SIMM. Tin sockets (or slots) should use tin edge connectors. The cost difference is minimal, but matching the metal type is critical.
Although it's true that gold won't corrode, a gold SIMM in a tin connector will produce much faster corrosion in the tin connectors. This quickly leads to random glitches and problems, so look at the board and match the color of the metal.
It's important to note, too, that each module is rated for the number of installations, or insertions. Each insertion causes scratches, and the more metal that is scratched off, the worse the connection becomes. In flea market exchanges and corporate environments, modules are subjected to constant wear and tear, and nobody is looking at the rated number of insertions.
Single Inline Memory Modules (SIMMs)
When DRAM chips were placed in a line on their own circuit board, it gave rise to the term inline memory. Once the chips were formed into a module, the entire module would fit into a socket on the board. These modules and sockets are referred to as memory banks. Depending on how the chips are connected on their own little circuit board, the module is called either a single, or dual inline memory module (SIMM or DIMM).
CAUTION
SIMMs come in both 30-pin and 72-pin versions. The 30-pin module is an 8-bit chip, with 1 optional parity bit. The 72-pin SIMM is a 32-bit chip, with 4 optional parity bits.
The memory bus grew from 8 bits to 16 bits and then from 32 bits to 64 bits wide. The 32-bit bus coincided with the development of a SIMM, which meant that the 32-bit-wide data bus could connect directly to 1 SIMM (4 sets of 8 bits). However, when the bus widened to 64 bits, rather than making a gigantic SIMM, we started using two SIMMs in a paired memory bank. The development of the 64-bit-wide DIMM superseded the SIMMs, and only used one module per socket again.
CAUTION
SIMMs and DIMMs are sometimes referred to as chips, but they are really a series of chips (modules). DRAM itself is a chip, and DRAM chips are grouped together to form SIMMs and DIMMs. SIMMs can come with a varying number of pins, including 30-pin and 72-pin. (Even though the 72-pin module could have chips on both sides, it was still a SIMM.)
Be careful when you read a question on the exam that you don't accidentally agree that a SIMM is a memory chip. A good way to keep alert is that chips have RAM in their name.
Dual Inline Memory Modules (DIMMs)
Dual inline memory modules are very similar to SIMMs, in that they install vertically into sockets on the system board. DIMMs are also a line of DRAM chips, combined on a circuit board. The main difference is that a DIMM has two different signal pins, one on each side of the module. This is why they are dual inline modules.
The differences between SIMMs and DIMMs are as follows:
DIMMs have opposing pins on either side of their board. The pins remain electrically isolated to form two separate contacts—a dual set of electrical contacts.
SIMMs also have opposing pins on either side of the board. However, the pins are connected, tying them together. The connection forms a single electrical contact.
DIMMs began to be used in computers that supported a 64-bit or wider memory bus. Pentium MMX, Pentium Pro, and Pentium II boards use 168-pin modules. They are 1 inch longer than 72-pin SIMMs, with a secondary keying notch so they'll only fit into their slots one way.
Don't Mix Different Types of Memory
Mixing different types of SIMMs or DIMMs within the same memory bank prevents the CPU from accurately detecting how much memory it has. In this case, the system will either fail to boot, or will boot and fail to recognize or use some of the memory.
You can, however, substitute a SIMM with a different speed within the same memory bank, but only if the replacement is equal to or faster than the replaced module.
All memory taken together (from all memory banks) will be set to the speed of the slowest SIMM.
Rambus Inline Memory Modules (RIMMs)
Rambus inline memory modules (RIMMs)—as opposed to dual inline—use Rambus Dyamic RAM (RDRAM) chips. Previously, on a standard bi-directional bus, data traveled down the bus in one direction, then returning data reversed back up the same bus in the opposite direction. It did this for each bank of memory, with each module being addressed separately. A wait occurred until the bus was ready for either the send or reverse.
RIMMs use a looped system, where everything is going in one direction (unidirectional). In a looped system, data moves forward from chip to chip and module to module. Data goes down the line, then the results data continues forward on the wire in the same direction. The results data doesn't have to wait for downstream data to finish being sent.
These chips are set on their modules contiguously (next to each other in a chain) and are connected to each other in a series. This means that, if an empty memory bank socket is in between two RIMM chips, you must install a continuity module, which is a low-cost circuit board that looks like a RIMM, but that doesn't have any chips. All it does is allows the current to move through the chain of RDRAM chips. It's like Christmas tree lights wired in series, where one bulb is missing.
NOTE
Latency is a combination of two things: You don't have to wait for the bus to turn around, and the cycle time is running at a fast 800MHz, so you don't have to wait very long for the next cycle. Using RDRAM chips, signals go from one module to the next to the next, and the throughput is triple that of 100MHz SDRAM. You can also use two to four RDRAM channels (narrow channel memory) at the same time. This can increase throughput to either 3.2GB or 6.4GB.
Why Memory Becomes Corrupted
Most DRAM chips in SIMMs or DIMMs require a parity bit because memory can be corrupted in the following two ways: Alpha particles can disturb memory cells with ionizing radiation, resulting in lost data, or electromagnetic interference (EMI) can change the stored information.
A DRAM cell (transistor) shares its storage charge with the bit line. This creates a small voltage differential, which can be sensed during read access. The differential can be influenced by other nearby bit line voltages. This, along with other electrical noise, can corrupt the electrical charge in the memory cell.
Supplementary Information
Throughout this book we've taken the time to explore technical details outside the scope of the A+ exam. In some instances, these supplementary segments serve as real-world examples of how the concepts you'll be tested on are used out in the field. In other instances, you should be aware that low level physics, electronics, engineering, and design schemes have produced long-term consequences. You'll be faced with questions that result from how modern computers have come to terms with these consequences, and you can either remember "just the facts," or have a sense of history as to how the facts came into being. If you choose, you may skip to the "Memory Diagnostics—Parity" section at this point.
The following section is a more technical examination of how Rambus memory went in one direction, and DDR memory went in another. Each type of memory develops problems based on RIMMs using serial transfers and DDR using parallel transfers. By seeing the problems, you should end up with a much better understanding of some of the other concepts covered in this book, and the underlying reasoning behind many of the exam questions. If you can figure out the reason for the question, many times you can also figure out the answer—even if you can't remember the specific details.
Serial Transfers and Latency
Aside from some other technical features we'll explore in a moment, RDRAM has a latency factor. In order to understand latency, let's take a look at the difference between serial and parallel transfers. We'll refer to these concepts again in Chapter 9, as they are fundamental concepts to computer technology. Think of a train, like the ones you often see in movies. When the hero has to chase the bad guy through the train, he starts at one end and goes from car to car. This is a serial process, where he moves through a series of cars. He begins at one end of a car, then walks all the way through it, usually looking for someone, and leaves by a door connecting to the next car in the series. Then the process starts all over again, until he either reaches the end of the train or someone gets killed.
Now suppose we take that same train, but this time we don't have a hero chasing a bad guy. Instead, let's imagine a train full of people on their way to work. If there was only one door at the back of the train, it would take forever when the train pulled into a station and everyone wanted to get off. To fix that problem, each car has its own door. When the train comes to a stop, everyone turns to the side facing the platform: The doors in each car open up, and a stream of people leaves each car simultaneously. This is a parallel transfer, with eight passengers leaving their own car in parallel (side by side) with each other.
One of the problems with Rambus memory is that the RIMMs are connected to the bus in a series. A data item has to pass through all the other modules before it reaches the memory bus. The signal has to travel a lot farther than it does on a DIMM, where the bus uses parallel transfers. The longer distance introduces a time lag, called latency. The longer the delay before the signal reaches the bus, the higher the latency. In a game, data generally moves in long streams, so serial transfers aren't a problem. But in a typical PC, data routinely moves in short bursts, and latency becomes a problem.
In a DDR or SDRAM system, each DIMM is connected, individually and in parallel, to the data bus. Regardless of whether the system uses a single DIMM or multiple DIMMs, transfer times are essentially the same. We'll discuss DDR memory at the end of this chapter.
Narrow Channel Bus
Earlier Pentiums had a data bus up to 64 bits wide and transferred data using a parallel process. The DIMM was also 64 bits wide, which meant that data could be moved across the memory bus in 64-bit chunks, or 8 bytes, per second. Remember that a byte is equal to 8 bits. Another way of looking at it is that a bit is one-eighth of a byte. Therefore, 64 bits divided by 8 equals 8 bytes.
All the memory systems that we've talked about are known as wide channel systems because the memory channel is equal to the width of the processor data bus. RDRAM is known as a narrow channel system because data is transferred only 2 bytes (16 bits) at a time. This might seem small, but those 2 bytes move extremely fast. The Rambus data bus is 18 bits wide, as opposed to the standard 32 or 64 bits, but the system sends data more frequently. It reads data on both the rising and falling edges of the clock signal, a process also used in Dynamic Data Rate (DDR) memory (discussed at the end of this segment).
Up until RDRAM, the fastest chips had a throughput of 100MHz. Remember that 8 megabytes moving in parallel means that 8MB is transferred every 1 second. At 100 clock ticks (cycles) per second, that means 100 times 8, or 800 megabytes per second. RDRAM chips move 2 megabytes per cycle (one on the up tick, one on the down tick). At 800MHz, that means RIMMs move 1,600MB per second (800 times 2 bytes), which translates to 1.66 gigabytes (GB) or a billion bytes—about twice as fast as SDRAM.
Another way to think of it is an example we heard, involving driving to the store. If you go out of your way, you can take 10 minutes to drive 10 miles on a highway at 60 mph. If you go directly to the store, you can take 4 minutes to drive only 2 miles at 30 mph. You might drive a whole lot faster on the highway, but you'll get to the store faster on the straight-line route. In this example, the store is the memory controller and bus.
Continuity Modules
Because Rambus memory works with serial transfers, all memory slots in the motherboard must have an installed module. Even if all the memory is contained in a single module, the unused sockets must have a PCB, known as a continuity module, to complete the circuit. This is similar to old strings of Christmas tree lights, wired in series, where every socket required a bulb. Since the current moved through each bulb in order to get to the next, a missing or burnt-out bulb would stop the flow of current to the entire string.
NOTE
One of the interesting things about very high-speed memory is that as signals move across the circuits in different ways, the modules begin to look more like microscopic networks. When we speak about network architectures in Chapter 8, we'll refer to signal interference as packets collide. This is similar to what's taking place in modern memory modules. At such high speeds, the physics of impedance and capacitance have more of an impact on the way data signals arrive at their destinations. Configuring a serial pathway has one set of problems, while parallel pathways have different problems. We won't go into all the low-level details, but you may find it interesting to do some research on the technical specifications of Rambus and DDR memory.
Double Data Rate SDRAM (DDR SDRAM)
DDR SDRAM probably won't be on the exam, but we'll mention it because technology is rapidly abandoning the previous types of SDRAM, along with RDRAM. Intel has stopped developing chipsets for RDRAM technology, and has shifted its resources to DDR SDRAM and DDR-II, using a newer version of the i845E chipset. Double Data Rate (DDR) came about as a response to RDRAM specifications put together by Intel and Rambus. Intel eventually bought Rambus and began licensing the technology for a fee. In much the way that IBM created Micro Channel Architecture (MCA) and charged a fee, both situations led to the development of separate consortiums for a different standard. DDR is an open architecture, and comes from a consortium of non-Intel manufacturers.
NOTE
DDR and Rambus memory are not backward compatible with SDRAM.
In our discussion of motherboards in Chapter 2, we mentioned that AMD developed faster processing by using a double-speed bus. Instead of using a full clock tick to run an event, they use a "half-tick" cycle, which is the voltage change during a clock cycle. In other words, as the clock begins a tick, the voltage goes up (an up tick) and an event takes place. When the clock ends the tick, the voltage goes down (a down tick) and a second event takes place. Therefore, every single clock cycle can have two memory cycle events. The AMD Athlon and Duron use the DDR specification with the double-speed bus.
DDR (double data rate) memory is the next generation SDRAM. Like SDRAM, DDR is synchronous with the system clock. The big difference between DDR and SDRAM memory is that DDR reads data on both the rising and falling edges of the clock tick. SDRAM only carries information on the rising edge of a signal. Basically, this allows the DDR module to transfer data twice as fast as SDRAM. For example, instead of a data rate of 133MHz, DDR memory transfers data at 266MHz.
DDR modules, like their SDRAM predecessors, are called DIMMs. They use motherboard system designs similar to those used by SDRAM; however, DDR is not backward compatible with SDRAM-designed motherboards. DDR memory supports both ECC (error correction code, typically used in servers) and nonparity (used on desktops/laptops.)
Aside from the royalty fee to Intel, Rambus memory is more expensive to produce than DDR SDRAM. DDR is designed around an open architecture, meaning no royalties. Rambus die (chips) are much larger than SDRAM or DDR die, which means that fewer parts can be produced on a wafer. Even so, Silicon Integrated Systems (SiS), the manufacturer of the first DDR400 chipset for the P4, has launched a PC1066 RDRAM system. Intel is still validating PC1066 support for the i850E chipset. DDR is the most popular DRAM at the moment, but RDRAM is still being used in a few high-end desktops and workstations.
RDRAM uses a 16-bit bus for the data signals, and this narrow 16-bit path is the main reason why RDRAM is able to run at speeds up to 533 MHz (with double data rate, an effective 1066 MHz). However, one of the problems with parallel transfers at high speeds is something called skew. The longer and faster the bus gets, the more likely it is that some data signals will arrive too soon or too late, based on the clock signal. This is where the very high speeds in today's systems are rekindling interest in serial transfers. The parallel port used to be the fastest port, but fast serial USB ports and serial ATA transfers (IDE drives, discussed in Chapter 6) are making parallel transfers seem out-of-date.
RDRAM also developed a different type of chip packaging, called Fine Pitch Ball Grid Array (FPBGA). Most DDR SDRAM uses a Thin Small Outline Package (TSOP). TSOP chips have fairly long contact pins on each side, as opposed to FPBGA chips, which have tiny ball contacts on the underside. The very small soldered balls have a much lower capacitive load than the TSOP pins. DDR SDRAM using the FPBGA packaging is able to run at 200-266MHz, whereas the same chips in a TSOP package are limited to 150-180MHz.
DDR-II and "Yellowstone"
DDR-II may be the end of Rambus memory, although people have speculated that RDRAM wouldn't last for quite some time. DDR-II extends the original DDR concept, taking on some of the advantages developed by Rambus. DDR-II uses FPBGA packaging for faster connection to the system, and reduces some of the signal reflection problems (stubs) of the original DDR. However, as bus speeds continue to increase, so too does latency. DDR-II is expected to enter the consumer market sometime in 2003. RDRAM is expected to continue to exist in 2003, but with very little chipset support. This makes it likely that DDR-II will take over from both DDR SDRAM and RDRAM.
The current PC1066 RDRAM can reach 667 MHz speeds (PC1333), so Samsung and Elpida have announced that they are studying 1333MHz RDRAM and even 800MHz memory (PC1600). These systems would most likely be used in high-end network systems, but that doesn't mean that RDRAM would be completely removed from the home consumer market. Rambus has already developed a new technology, codenamed "Yellowstone," which should reach 400MHz, using octal data rates. This may lead to 3.2GHz memory, with a 12.4GB/s throughput. With a 128 bit interface Rambus promises to achieve 100GB/s throughput. Yellowstone technology is expected to arrive in game boxes first, with PC memory scheduled for sometime around 2005.